The development of the integrated circuit industry is inclined towards multi-chip integration. A three-dimensional (3D) integrated circuit (IC) in a stacked package has a reduced routing length among chips and shortened signal transmission time among chips, and has thus become one of the mainstream technologies. In the three-dimensional integrated circuit technology, through-silicon vias (TSV) and bumps can provide interconnections among chips, and may also serve as power sources.
However, process yield of TSVs and bumps are currently rather low. The reliability of a power delivery network (PDN) of a chip is hence degraded while production cost of the integrated circuit is increased.
Therefore, there is a need for a solution that simulates and identifies in advance a power source likely causing a fault in the PDN and provides associated information as reference for subsequently repairing/reinforcing the PDN, so as to enhance the reliability of the PDN.